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This commit is contained in:
Imants Pulkstenis
2019-07-11 18:01:21 +03:00
commit d18a10f6ea
51 changed files with 85956 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
com_to_mem_tb.v
+487
View File
@@ -0,0 +1,487 @@
// This file is Test Bench for UART to memory module
// its simulates UART comands sent to FPGA to
// write in memmory address value.
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
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`include "UART_RX.v"
`include "clock_divider_param.v"
`include "clock_enable_param.v"
`include "bram.v"
`include "7segment.v"
`include "com_to_mem_FSM_hex.v"
`include "com_to_mem_top.v"
module com_to_mem_tb();
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wire [6:0] seg;
wire [3:0] an;
reg sw=1'b1;
//wire dp;
// 50% duty cycle clock
always #0.5 clk <= ~clk;
initial begin
// starting UART transition
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$display(" ");
$display("Use this command to open timing diagram:");
$display("gtkwave -f wave.vcd");
$display("----------------------------------------------");
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
end
top Test_Unit(
.clk(clk),
.sw(sw),
.RsRx(RsRx),
.RsTx(RsTx),
.led(led),
.seg(seg),
.an(an)//,
// .dp(dp)
);
endmodule