105 lines
4.2 KiB
Verilog
105 lines
4.2 KiB
Verilog
// fpga4student.com: FPGA projects, Verilog projects, VHDL projects
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// FPGA tutorial: How to interface a mouse with Basys 3 FPGA
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// Verilog code for interfacing a mouse with the Basys 3 FPGA board
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module mouse_basys3_FPGA(
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input clock_100Mhz, // 100 Mhz clock source on Basys 3 FPGA
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input reset, // reset
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input Mouse_Data, // Mouse PS2 data
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input Mouse_Clk, // Mouse PS2 Clock
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output reg [3:0] Anode_Activate, // anode signals of the 7-segment LED display
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output reg [6:0] LED_out// cathode patterns of the 7-segment LED display
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);
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reg [5:0] Mouse_bits; // count number of bits receiving from the PS2 mouse
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reg [26:0] one_second_counter; // counter for generating 1 second clock enable
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wire one_second_enable;// one second enable for counting numbers
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reg [15:0] displayed_number; // Number to be increased and decreased by the mouse
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reg [3:0] LED_BCD;
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// Signals for displaying on 7-segment LED of Basys 3 FPGA
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reg [20:0] refresh_counter; // the first 19-bit for creating 190Hz refresh rate
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// the other 2-bit for creating 4 LED-activating signals
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wire [1:0] LED_activating_counter;
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// counting the number of bits receiving from the Mouse Data
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// 33 bits to be received from the Mouse
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always @(posedge Mouse_Clk or posedge reset)
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begin
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if(reset==1)
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Mouse_bits <= 0;
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else if(Mouse_bits <=31)
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Mouse_bits <= Mouse_bits + 1;
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else
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Mouse_bits <= 0;
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end
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// Increase/Decrease the number when pressing Left/Right Mouse
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always @(negedge Mouse_Clk or posedge reset)
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begin
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if(reset)
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displayed_number <= 0;
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else begin
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if(Mouse_bits==1) begin
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if(Mouse_Data==1) // if The mouse is left clicked, increase the number
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displayed_number <= displayed_number + 1;
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end
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else if(Mouse_bits==2) begin
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if(Mouse_Data==1&&displayed_number>0)// if The mouse is right clicked, decrease the number
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displayed_number <= displayed_number - 1;
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end
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end
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end
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// refreshing the 4-digit 7-segment display on Basys 3 FPGA
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always @(posedge clock_100Mhz or posedge reset)
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begin
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if(reset==1)
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refresh_counter <= 0;
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else
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refresh_counter <= refresh_counter + 1;
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end
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assign LED_activating_counter = refresh_counter[20:19];
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// anode activating signals for 4 LEDs
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// decoder to generate anode signals
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always @(*)
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begin
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case(LED_activating_counter)
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2'b00: begin
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Anode_Activate = 4'b0111;
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// activate LED1 and Deactivate LED2, LED3, LED4
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LED_BCD = displayed_number/1000;
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// the first digit of the 16-bit number
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end
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2'b01: begin
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Anode_Activate = 4'b1011;
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// activate LED2 and Deactivate LED1, LED3, LED4
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LED_BCD = (displayed_number % 1000)/100;
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// the second digit of the 16-bit number
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end
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2'b10: begin
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Anode_Activate = 4'b1101;
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// activate LED3 and Deactivate LED2, LED1, LED4
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LED_BCD = ((displayed_number % 1000)%100)/10;
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// the third digit of the 16-bit number
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end
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2'b11: begin
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Anode_Activate = 4'b1110;
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// activate LED4 and Deactivate LED2, LED3, LED1
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LED_BCD = ((displayed_number % 1000)%100)%10;
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// the fourth digit of the 16-bit number
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end
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endcase
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end
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// Cathode patterns of the 7-segment LED display
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always @(*)
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begin
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case(LED_BCD)
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4'b0000: LED_out = 7'b0000001; // "0"
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4'b0001: LED_out = 7'b1001111; // "1"
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4'b0010: LED_out = 7'b0010010; // "2"
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4'b0011: LED_out = 7'b0000110; // "3"
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4'b0100: LED_out = 7'b1001100; // "4"
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4'b0101: LED_out = 7'b0100100; // "5"
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4'b0110: LED_out = 7'b0100000; // "6"
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4'b0111: LED_out = 7'b0001111; // "7"
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4'b1000: LED_out = 7'b0000000; // "8"
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4'b1001: LED_out = 7'b0000100; // "9"
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default: LED_out = 7'b0000001; // "0"
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endcase
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end
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endmodule |