79 lines
2.2 KiB
Verilog
79 lines
2.2 KiB
Verilog
module vga_module#(
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parameter
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ADDR_WIDTH = 13,
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DATA_WIDTH = 12,
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DEPTH = 4_800, // 307_200,//
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HSYNC_CLKS = 800,
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HSYNC_DISPLAY = 640,
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HSYNC_PULSE = 96,
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HSYNC_FRONT_PORCH = 16,
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HSYNC_BACK_PORCH = 48,
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VSYNC_LINES = 521,
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VSYNC_DISPLAY = 480,
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VSYNC_PULSE = 2,
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VSYNC_FRONT_PORCH = 10,
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VSYNC_BACK_PORCH = 29
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)(
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input clk,
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output [3:0] o_vgaRed,
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output [3:0] o_vgaBlue,
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output [3:0] o_vgaGreen,
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output o_Hsync,
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output o_Vsync,
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output o_display,
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output [3:0] o_line_mux,
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output [ADDR_WIDTH-1:0] o_addr_rd,
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input [DATA_WIDTH-1:0] i_data_rd
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);
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//-------Internal registers and wires--------------
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wire w_v_display;
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wire w_h_display;
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wire [9:0] column;
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wire [8:0] line;
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//-------sub modules-------------------------------
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horizontal_counter #(
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.HSYNC_CLKS(HSYNC_CLKS) ,
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.HSYNC_DISPLAY(HSYNC_DISPLAY) ,
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.HSYNC_PULSE(HSYNC_PULSE) ,
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.HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH) ,
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.HSYNC_BACK_PORCH(HSYNC_BACK_PORCH)
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) horizontal_counter1 (
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.clk(clk),
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.o_Hsync(o_Hsync),
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.o_h_display(w_h_display),
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.o_h_pixel(column)
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);
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vertical_counter #(
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.VSYNC_LINES(VSYNC_LINES) ,
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.VSYNC_DISPLAY(VSYNC_DISPLAY) ,
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.VSYNC_PULSE(VSYNC_PULSE) ,
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.VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
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.VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
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) vertical_counter1 (
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//.clk(clk),
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.i_Hsync(o_Hsync),
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.o_Vsync(o_Vsync),
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.o_v_display(w_v_display),
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.o_v_line(line)
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);
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assign o_display = (w_v_display && w_h_display) ;
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assign o_vgaRed = o_display ? i_data_rd[11:8] : 4'h0;
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assign o_vgaBlue = o_display ? i_data_rd[3:0] : 4'h0;
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assign o_vgaGreen = o_display ? i_data_rd[7:4] : 4'h0;
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/*
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assign o_addr_rd = (((line*HSYNC_DISPLAY) + column + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?
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'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + column[9:1] + 1 ; // get next pixel
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*/
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assign o_addr_rd =
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((line[8:5]) * 'd320 ) + column[9:1];// + 1;
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//assign o_line_mux = line[8:5];
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assign o_line_mux = line[4:1];
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endmodule |