73 lines
2.2 KiB
Verilog
73 lines
2.2 KiB
Verilog
module vertical_counter #(
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parameter
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VSYNC_LINES = 521,
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VSYNC_DISPLAY = 480,
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VSYNC_PULSE = 2,
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VSYNC_FRONT_PORCH = 10,
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VSYNC_BACK_PORCH = 29
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)(
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//input clk,
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input i_Hsync,
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output o_Vsync,
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output o_v_display,
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output [8:0] o_v_line
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);
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//----------Internal registers, constants and wariables-----
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reg vsync_reg = 1'b1;
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reg [9:0] counter_reg = 'h0;
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reg [8:0] counter_line_reg = 'h0;
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reg [2:0] r_state=VS_FRONT_PORCH, r_next=VS_FRONT_PORCH;
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localparam [2:0] VS_FRONT_PORCH = 'h0,
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VS_PULSE = 'h1,
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VS_BACK_PORCH = 'h2,
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VS_DISPLAY = 'h3;
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//---------state register sequential always block-----------
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always @(posedge i_Hsync ) begin
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r_state <= r_next;
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end
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//----next state & outputs, combinational always block------
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always@(posedge i_Hsync) begin
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counter_reg <= counter_reg + 1;
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case (r_state)
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VS_FRONT_PORCH: begin
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vsync_reg <= 1'b1;
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if(counter_reg == VSYNC_FRONT_PORCH - 2)
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r_next <= VS_PULSE;
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end
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VS_PULSE:begin
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vsync_reg <= 1'b0;
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if(counter_reg == VSYNC_FRONT_PORCH +
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VSYNC_PULSE - 2)
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r_next <= VS_BACK_PORCH;
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end
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VS_BACK_PORCH:begin
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vsync_reg <= 1'b1;
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if(counter_reg == VSYNC_FRONT_PORCH +
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VSYNC_PULSE +
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VSYNC_BACK_PORCH - 2) begin
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r_next <= VS_DISPLAY;
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counter_line_reg <= 'h0;
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end
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end
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VS_DISPLAY:begin
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vsync_reg <= 1'b1;
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counter_line_reg <= counter_line_reg + 1;
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if(counter_reg == VSYNC_FRONT_PORCH +
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VSYNC_PULSE +
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VSYNC_BACK_PORCH +
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VSYNC_DISPLAY - 1) begin
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r_next <= VS_FRONT_PORCH;
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counter_reg <= 'h0;
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end
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end
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endcase
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end
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assign o_Vsync = vsync_reg;
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assign o_v_display = (counter_line_reg >= 1 && counter_line_reg <= VSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
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assign o_v_line = counter_line_reg - 1 ;
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endmodule |