103 lines
2.0 KiB
Verilog
103 lines
2.0 KiB
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "clock_divider_param.v"
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`include "clock_enable_param.v"
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`include "blockram.v"
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`include "pattern_gen.v"
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`include "vga_module.v"
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`include "horizontal_counter.v"
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`include "vertical_counter.v"
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// `include "UART_Loopback_module.v"
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// `include "UART_TX.v"
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// `include "UART_RX.v"
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// `include "7segment.v"
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// `include "com_to_mem_FSM_hex.v"
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// `include "com_to_mem_module.v"
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// `include "debounce_switch.v"
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`include "mux.v"
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//top module
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`include "top.v"
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module top_tb#( parameter
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WAIT = 1,
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WAIT_WIDTH = 2//,
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// SPEED = 2,
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// //memory parameters
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// ADDR_WIDTH = 17, //19, //
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// DATA_WIDTH = 12,
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// DEPTH = 307_200//76_800, //
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)();
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reg clk = 1'b0;
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// reg pclk = 1'b0;
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// reg hs = 1'b0;
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// reg vs = 1'b0;
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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// always #2 pclk <= ~pclk;
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// always #100 hs <= 1;
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// always #102 hs <= 0;
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// always #200 vs <= 1;
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// always #202 vs <= 0;
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// reg RsRx;
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// wire RsTx;
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top #(
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// .SPEED(SPEED),
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// .ADDR_WIDTH(ADDR_WIDTH),
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// .DATA_WIDTH(DATA_WIDTH),
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// .DEPTH(DEPTH)
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)Test_Unit(
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.clk(clk)//,
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// .RsRx(RsRx),
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// .RsTx(RsTx),
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// .sw(3'b101),
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// .ov7670_cam1_pclk(pclk),
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// .ov7670_cam2_pclk(pclk),
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// .ov7670_cam1_vs(vs),
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// .ov7670_cam1_hs(hs),
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// .ov7670_cam2_vs(vs),
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// .ov7670_cam2_hs(hs),
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// .im_p(9'b00_01_01_000)
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);
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// initial begin
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// end
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initial begin
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$display("*");
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#030_000;
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$display("*");
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |