175 lines
6.7 KiB
Verilog
175 lines
6.7 KiB
Verilog
////////////////////////////////////////////
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//
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// | Sign | Exponent | Mantissa |
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// | 1bit | 8bits | 18bits |
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//
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// 2^0 => Exponent = 'd127 = 'h7f
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//
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// Mantissa = [ ( 1-2^(-126) ) ; 0.5 ]
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//
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////////////////////////////////////////////
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module summ #(
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parameter
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SIGN_WIDTH = 1,
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EXPONENT_WIDTH = 8,
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MANTISSA_WIDTH = 18,
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SIZE = 2 // size for for registers FSM
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)
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(
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input clk,
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input [ 26 :0] input_a,
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input [ 26 :0] input_b,
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input start,
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output [ 26 :0] output_q,
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output done,
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output overflow,
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output underflow
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);
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//-------------Internal Constants---------------------------
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localparam [SIZE-1 :0] IDLE = 'h0,
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SHIFT = 'h1,
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SUMM = 'h2,
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NORM = 'h3;
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reg [SIZE-1:0] r_state=IDLE,
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r_next=IDLE;
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reg [ 18 :0 ] r_large_mantissa1 = 'b0,
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r_small_mantissa1 = 'b0,
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r_large_mantissa2 = 'b0,
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r_small_mantissa2 = 'b0,
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r_large_mantissa3 = 'b0,
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r_small_mantissa3 = 'b0,
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r_large_mantissa4 = 'b0,
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r_small_mantissa4 = 'b0;
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reg [ 7 :0 ] r_large_exponent1 = 'b0,
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r_large_exponent2 = 'b0,
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r_large_exponent3 = 'b0,
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r_large_exponent4 = 'b0;
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reg r_large_sign = 'b0,
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r_small_sign = 'b0;
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reg [ 7 :0 ] r_delta_exponent = 'b0;
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reg r_done = 'b0;
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reg r_overflow = 'b0;
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reg r_underflow = 'b0;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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r_state <= r_next;
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end
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//----next state & outputs, combinational always block------
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always@(posedge clk) begin
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case(r_state)
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IDLE :
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begin
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r_done <= 'b0;
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if (start == 1'b1)
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begin
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if (input_a[25:18] > input_b[25:18])
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begin
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r_large_mantissa1 <= input_a[17:0];
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r_small_mantissa1 <= input_b[17:0];
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r_large_exponent1 <= input_a[25:18];
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//r_small_exponent <= input_b[25:18];
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r_large_sign <= input_a[26];
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r_small_sign <= input_a[26];
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r_delta_exponent <= input_a[25:18] - input_b[25:18];
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r_next <= SHIFT;
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end
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else if (input_a[25:18] < input_b[25:18])
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begin
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r_large_mantissa1 <= input_b[17:0];
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r_small_mantissa1 <= input_a[17:0];
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r_large_exponent1 <= input_b[25:18];
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//r_small_exponent <= input_a[25:18];
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r_large_sign <= input_b[26];
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r_small_sign <= input_a[26];
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r_delta_exponent <= input_b[25:18] - input_a[25:18];
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r_next <= SHIFT;
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end
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else if (input_a[25:18] == input_b[25:18])
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begin
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r_large_mantissa1 <= input_a[17:0];
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r_small_mantissa1 <= input_b[17:0];
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r_large_exponent1 <= input_a[25:18];
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//r_small_exponent <= input_b[25:18];
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r_large_sign <= input_a[26];
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r_small_sign <= input_a[26];
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r_next <= SUMM;
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end
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end
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end
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SHIFT :
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begin
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r_next <= SUMM;
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case(r_delta_exponent)
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'd1 : r_small_mantissa2 <= r_small_mantissa1 >> 1;
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'd2 : r_small_mantissa2 <= r_small_mantissa1 >> 2;
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'd3 : r_small_mantissa2 <= r_small_mantissa1 >> 3;
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'd4 : r_small_mantissa2 <= r_small_mantissa1 >> 4;
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'd5 : r_small_mantissa2 <= r_small_mantissa1 >> 5;
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'd6 : r_small_mantissa2 <= r_small_mantissa1 >> 6;
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'd7 : r_small_mantissa2 <= r_small_mantissa1 >> 7;
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'd8 : r_small_mantissa2 <= r_small_mantissa1 >> 8;
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'd9 : r_small_mantissa2 <= r_small_mantissa1 >> 9;
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'd10 : r_small_mantissa2 <= r_small_mantissa1 >> 10;
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'd11 : r_small_mantissa2 <= r_small_mantissa1 >> 11;
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'd12 : r_small_mantissa2 <= r_small_mantissa1 >> 12;
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'd13 : r_small_mantissa2 <= r_small_mantissa1 >> 13;
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'd14 : r_small_mantissa2 <= r_small_mantissa1 >> 14;
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'd15 : r_small_mantissa2 <= r_small_mantissa1 >> 15;
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'd16 : r_small_mantissa2 <= r_small_mantissa1 >> 16;
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'd17 : r_small_mantissa2 <= r_small_mantissa1 >> 17;
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default : r_small_mantissa2 <= 0; // if number is to small result is larger number
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endcase
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end
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SUMM :
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begin
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r_next <= NORM;
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case(r_large_sign == r_small_sign)
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1'b1 : r_large_mantissa3 <= r_large_mantissa2 + r_small_mantissa2;
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1'b0 : r_large_mantissa3 <= r_large_mantissa2 - r_small_mantissa2;
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endcase
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end
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NORM :
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begin
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r_next <= IDLE;
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r_done <= 'b1;
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if (r_large_mantissa[18])
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begin
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r_large_mantissa4 <= r_large_mantissa3 >> 1;
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if (r_large_exponent < 255)
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begin r_large_exponent <= r_large_exponent + 1; end
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else
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begin r_overflow <= 1; end
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end
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else if (r_large_mantissa[17])
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begin
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r_large_mantissa4 <= r_large_mantissa3 << 1;
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if (r_large_exponent > 0)
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begin r_large_exponent <= r_large_exponent - 1; end
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else
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begin r_underflow <= 1; end
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end
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end
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default : r_next <= IDLE; // on error
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endcase
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end
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//-------------------- assignning combionational logic----------------------------
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assign done = r_done;
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assign output_q = { r_large_sign, r_large_exponent4[7:0], r_large_mantissa4[17:0] };
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endmodule |