84 lines
1.9 KiB
Verilog
84 lines
1.9 KiB
Verilog
// This module generates color patherns and rwite them in
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// BlockRAM memory
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//
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module pattern_gen #( parameter
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LINES = 16,
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COLUMNS = 320,
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DEPTH = 76_800, //307_200, //
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ADDR_WIDTH = 17,
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DATA_WIDTH = 12,
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SPEED = 2,
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SIZE = 2
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)(
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input clk,
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input i_enable,
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output [ADDR_WIDTH-1:0] o_addr,
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output [DATA_WIDTH-1:0] o_data,
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output o_write);
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//-------------Internal Constants---------------------------
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reg [31:0] speed_counter_reg = 'b0;
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// reg [3:0] red_reg = 'b0;
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// reg [3:0] blue_reg = 'b0;
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// reg [3:0] green_reg = 'b0;
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reg [8:0] line_reg = 'b0;
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reg [9:0] column_reg = 'b0;
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reg write_reg=1'b0;
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// always @(posedge clk) begin
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// speed_counter_reg <= speed_counter_reg + 1;
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// end
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always @(posedge clk) begin
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// speed_counter_reg <= speed_counter_reg + 1;
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// if(speed_counter_reg == SPEED ) begin
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// if(i_enable) begin
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write_reg <= 1'b1;
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speed_counter_reg <= 0;
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if(column_reg < COLUMNS-1) begin
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column_reg <= column_reg + 1 ;
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end
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else begin
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column_reg <= 0;
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if (line_reg< LINES -1 ) begin
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line_reg <= line_reg + 1;
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end
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else begin
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line_reg <= 0;
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end
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end
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// end
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// end
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// else // if (i_enable)
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// write_reg <= 1'b0;
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end
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// always@* begin
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// if (line_reg < 239 ) begin
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// green_reg <= 4'b1111;
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// end
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// else begin
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// green_reg <= 4'b0000;
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// end
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// if (column_reg > 319 ) begin
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// red_reg <= 4'b1111;
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// end
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// else begin
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// red_reg <= 4'b0000;
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// end
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// end
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assign o_addr = (line_reg * COLUMNS) + column_reg ;
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assign o_data = {line_reg[3:0], line_reg[3:0], line_reg[3:0]};//{green_reg, red_reg , blue_reg};
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assign o_write = write_reg;
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endmodule |