88 lines
1.9 KiB
Verilog
88 lines
1.9 KiB
Verilog
`timescale 10 ns / 1ns
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`include "mux.v"
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module mux_tb#( parameter
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SELECT_WIDTH = 4,
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DATA_WIDTH = 12
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) ();
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reg [DATA_WIDTH-1:0] w_data_rd = 10;
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reg [DATA_WIDTH-1:0] w_data_rd0 = 14;
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reg [DATA_WIDTH-1:0] w_data_rd1 = 4;
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reg [DATA_WIDTH-1:0] w_data_rd2 = 23;
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reg [DATA_WIDTH-1:0] w_data_rd3 = 5;
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reg [DATA_WIDTH-1:0] w_data_rd4 = 6;
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reg [DATA_WIDTH-1:0] w_data_rd5 = 8;
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reg [DATA_WIDTH-1:0] w_data_rd6 = 12;
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reg [DATA_WIDTH-1:0] w_data_rd7 = 23;
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reg [DATA_WIDTH-1:0] w_data_rd8 = 23;
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reg [DATA_WIDTH-1:0] w_data_rd9 = 1;
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reg [DATA_WIDTH-1:0] w_data_rd10 = 2;
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reg [DATA_WIDTH-1:0] w_data_rd11 = 3;
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reg [DATA_WIDTH-1:0] w_data_rd12 = 22;
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reg [DATA_WIDTH-1:0] w_data_rd13 = 33;
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reg [DATA_WIDTH-1:0] w_data_rd14 = 44;
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reg [SELECT_WIDTH-1:0] w_vga_line_mux=0;
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// 50% duty cycle clock
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//always #0.5 clk <= ~clk;
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initial begin
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// starting
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//
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#1 w_vga_line_mux<=1;
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#1 w_vga_line_mux<=2;
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#1 w_vga_line_mux<=3;
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#1 w_vga_line_mux<=4;
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#1 w_vga_line_mux<=5;
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#1 w_vga_line_mux<=6;
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#1 w_vga_line_mux<=7;
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#1 w_vga_line_mux<=8;
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#1 w_vga_line_mux<=9;
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#1 w_vga_line_mux<=10;
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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mux #(
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.DATA_WIDTH(DATA_WIDTH),
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.SELECT_WIDTH(SELECT_WIDTH))
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UnitUnderTest(
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.select(w_vga_line_mux),
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.d0(w_data_rd0),
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.d1(w_data_rd1),
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.d2(w_data_rd2),
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.d3(w_data_rd3),
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.d4(w_data_rd4),
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.d5(w_data_rd5),
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.d6(w_data_rd6),
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.d7(w_data_rd7),
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.d8(w_data_rd8),
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.d9(w_data_rd9),
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.d10(w_data_rd10),
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.d11(w_data_rd11),
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.d12(w_data_rd12),
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.d13(w_data_rd13),
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.d14(w_data_rd14),
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.o_q());
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endmodule |