92 lines
1.7 KiB
Verilog
92 lines
1.7 KiB
Verilog
////////////////////////////////////////////
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//
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// | Sign | Exponent | Mantissa |
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// | 1bit | 8bits | 18bits |
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//
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// 2^0 => Exponent = 'd127 = 'h7f
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//
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// Mantissa = [ ( 1-2^(-126) ) ; 0.5 ]
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//
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////////////////////////////////////////////
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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`include "multiply.v"
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module multiply_tb ();
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// 50% duty cycle clock
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reg clk = 1'b1;
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always #0.5 clk <= ~clk;
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reg [26 : 0 ] reg_input_a = 0;
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reg [26 : 0 ] reg_input_b = 0;
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initial begin
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#100
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reg_input_a = 27'h5FE0000;
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reg_input_b = 27'h1FE0000;
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#100
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reg_input_a = 27'h13E8083;
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reg_input_b = 27'h13E8083;
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#100
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reg_input_a = 27'h0E2194D;
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reg_input_b = 27'h0E2194D;
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#100
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reg_input_a = 27'h20A0000;
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reg_input_b = 27'h0E2194D;
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#100
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reg_input_a = 27'h20A0000;
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reg_input_b = 27'h2020000;
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#100
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reg_input_a = 27'h226A800;
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reg_input_b = 27'h6270C00;
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#100
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reg_input_a = 27'h64E05F8;
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reg_input_b = 27'h1FE0000;
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#100
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reg_input_a = 27'h64A05F8;
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#100
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reg_input_b = 27'h64A05F8;
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#1000
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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multiply Test_Unit(
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.clk(clk),
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.input_a(reg_input_a),
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.input_b(reg_input_b),
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.output_q(),
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.underflow()
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);
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endmodule |