66 lines
2.1 KiB
Verilog
66 lines
2.1 KiB
Verilog
////////////////////////////////////////////
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//
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// | Sign | Exponent | Mantissa |
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// | 1bit | 8bits | 18bits |
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//
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// 2^0 => Exponent = 'd127 = 'h7f
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//
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// Mantissa = [ ( 1-2^(-126) ) ; 0.5 ]
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//
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////////////////////////////////////////////
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module multiply #(
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parameter
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SIGN_WIDTH = 1,
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EXPONENT_WIDTH = 8,
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MANTISSA_WIDTH = 18
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)
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(
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input clk,
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input [ 26 :0] input_a,
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input [ 26 :0] input_b,
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output [ 26 :0] output_q,
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output underflow
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);
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reg [35 : 0 ] reg_multiply = 0; // for mantissa
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reg [8 : 0 ] reg_summ1 = 0; // for exponent
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reg [8 : 0 ] reg_summ2 = 0; // for exponent if reg_multiply smaler then 0.5(decimal)
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reg reg_sign = 0; // for sign
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reg [17 : 0 ] reg_mantissa1 = 0;
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reg [17 : 0 ] reg_mantissa2 = 0; // if reg_multiply smaler then 0.5(decimal)
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reg [8 : 0 ] reg_summ3 = 0; // use in comarison and testbench
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always@(posedge clk) begin
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if (input_a[17:0] == 0 || input_b[17:0] == 0) begin // if one of numbers are 0
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reg_multiply <= 0;
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reg_summ1 <= 0 ;
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reg_summ2 <= 0 ;
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reg_sign <= 0;
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end
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else begin
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reg_multiply <= input_a[17:0] * input_b[17:0]; // multiply mantisa
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reg_summ1 <= input_a[25:18] + input_b[25:18] - 8'h7F ; // add exponents
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reg_summ2 <= input_a[25:18] + input_b[25:18] - 8'h80 ;
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reg_sign <= input_a[26] ^ input_b[26]; // determine sign of resulting number
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end
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end
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always@* begin
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reg_mantissa1 <= reg_multiply >> 18 ;
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reg_mantissa2 <= reg_multiply >> 17 ; // if reg_multiply smaler then 0.5(decimal)
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reg_summ3 <= input_a[25:18] + input_b[25:18]; // use in comparison and testbench
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end
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assign underflow = reg_summ3 < 8'h7F
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? 1'b1 : 1'b0 ;
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assign output_q = reg_multiply[35] ?
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{ reg_sign , reg_summ1[7:0] , reg_mantissa1[17:0] }
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:
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{ reg_sign , reg_summ2[7:0] , reg_mantissa2[17:0] }
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;
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endmodule |