61 lines
900 B
Verilog
61 lines
900 B
Verilog
`include "clock_enable_param.v"
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module clock_enable_tb();
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reg clk = 1'b0;
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wire enable0;
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wire enable1;
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wire enable2;
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wire enable3;
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always #1 clk <= ~clk;
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initial
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begin
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#100;
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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clock_enable_param test_unit0(
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.clk(clk),
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.enable(enable0)
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);
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clock_enable_param #(
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.WAIT(2),
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.WIDTH(4)
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) test_unit1(
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.clk(clk),
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.enable(enable1)
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);
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clock_enable_param #(
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.WAIT(3),
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.WIDTH(8)
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)test_unit2(
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.clk(clk),
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.enable(enable2)
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);
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clock_enable_param #(
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.WAIT(9),
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.WIDTH(8)
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)test_unit3(
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.clk(clk),
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.enable(enable3)
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);
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endmodule |