40 lines
650 B
Verilog
40 lines
650 B
Verilog
// `timescale [time unit] / [time precision]
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`timescale 10 ps / 1 ps
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`include "clock_divider_param.v"
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module clock_divider_param_tb ();
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reg clk = 1'b0;
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wire enable;
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always #1 clk <= ~clk;
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initial
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begin
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#100;
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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clock_divider #(
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.DIVIDER(2),
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.WIDTH(2)
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) test_unit1 (
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.clk(clk),
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.enable(enable)
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);
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endmodule |