147 lines
3.8 KiB
Verilog
147 lines
3.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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// File Downloaded from http://www.nandland.com
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//////////////////////////////////////////////////////////////////////
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// This file contains the UART Transmitter. This transmitter is able
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// to transmit 8 bits of serial data, one start bit, one stop bit,
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// and no parity bit. When transmit is complete o_Tx_done will be
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// driven high for one clock cycle.
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//
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// Set Parameter CLKS_PER_BIT as follows:
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// CLKS_PER_BIT = (Frequency of clk)/(Frequency of UART)
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// Example: 25 MHz Clock, 115200 baud UART
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// (25000000)/(115200) = 217
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module UART_TX
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#(parameter CLKS_PER_BIT = 217)
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(
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input clk,
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input i_TX_DV,
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input [7:0] i_TX_Byte,
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output o_TX_Active,
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output reg o_TX_Serial,
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output o_TX_Done
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);
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localparam IDLE = 3'b000;
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localparam TX_START_BIT = 3'b001;
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localparam TX_DATA_BITS = 3'b010;
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localparam TX_STOP_BIT = 3'b011;
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localparam CLEANUP = 3'b100;
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reg [2:0] r_SM_Main = 0;
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reg [9:0] r_Clock_Count = 0;
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reg [2:0] r_Bit_Index = 0;
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reg [7:0] r_TX_Data = 0;
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reg r_TX_Done = 0;
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reg r_TX_Active = 0;
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always @(posedge clk)
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begin
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case (r_SM_Main)
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IDLE :
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begin
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o_TX_Serial <= 1'b1; // Drive Line High for Idle
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r_TX_Done <= 1'b0;
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r_Clock_Count <= 0;
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r_Bit_Index <= 0;
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if (i_TX_DV == 1'b1)
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begin
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r_TX_Active <= 1'b1;
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r_TX_Data <= i_TX_Byte;
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r_SM_Main <= TX_START_BIT;
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end
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else
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r_SM_Main <= IDLE;
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end // case: IDLE
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// Send out Start Bit. Start bit = 0
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TX_START_BIT :
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begin
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o_TX_Serial <= 1'b0;
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// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
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if (r_Clock_Count < CLKS_PER_BIT)
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begin
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r_Clock_Count <= r_Clock_Count + 1;
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r_SM_Main <= TX_START_BIT;
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end
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else
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begin
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r_Clock_Count <= 0;
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r_SM_Main <= TX_DATA_BITS;
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end
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end // case: TX_START_BIT
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// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
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TX_DATA_BITS :
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begin
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o_TX_Serial <= r_TX_Data[r_Bit_Index];
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1;
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r_SM_Main <= TX_DATA_BITS;
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end
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else
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begin
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r_Clock_Count <= 0;
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// Check if we have sent out all bits
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if (r_Bit_Index < 7)
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begin
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r_Bit_Index <= r_Bit_Index + 1;
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r_SM_Main <= TX_DATA_BITS;
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end
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else
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begin
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r_Bit_Index <= 0;
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r_SM_Main <= TX_STOP_BIT;
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end
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end
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end // case: TX_DATA_BITS
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// Send out Stop bit. Stop bit = 1
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TX_STOP_BIT :
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begin
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o_TX_Serial <= 1'b1;
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// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1;
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r_SM_Main <= TX_STOP_BIT;
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end
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else
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begin
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r_TX_Done <= 1'b1;
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r_Clock_Count <= 0;
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r_SM_Main <= CLEANUP;
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r_TX_Active <= 1'b0;
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end
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end // case: TX_STOP_BIT
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// Stay here 1 clock
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CLEANUP :
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begin
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r_TX_Done <= 1'b1;
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r_SM_Main <= IDLE;
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end
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default :
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r_SM_Main <= IDLE;
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endcase
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end
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assign o_TX_Active = r_TX_Active;
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assign o_TX_Done = r_TX_Done;
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endmodule
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