54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
`include "UART_Loopback_module.v"
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`include "UART_TX.v"
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`include "UART_RX.v"
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module UART_Loopback_tb();
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reg clk = 1'b1;
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reg RsRx; // UART RX Data
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wire RsTx; // UART TX Data
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wire [7:0] dout; // data out
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wire o_TX_Done; // high when transition is done
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wire o_RX_DV; // data valid
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always #1 clk <= ~clk;
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initial begin
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// starting UART transition
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#0 RsRx = 1;
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#1736 RsRx = 0;
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#1736 RsRx = 1;
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#1736 RsRx = 0;
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#1736 RsRx = 1;
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#1736 RsRx = 0;
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#1736 RsRx = 1;
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#1736 RsRx = 0;
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#1736 RsRx = 1;
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#1736 RsRx = 0;
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#1736 RsRx = 1;
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#100_000;
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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UART_Loopback_module Test_Unit(
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.clk(clk),
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.RsRx(RsRx),
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.RsTx(RsTx),
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.dout(dout),
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.o_TX_Done(o_TX_Done),
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.o_RX_DV(o_RX_DV)
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);
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endmodule |